The present invention relates to a system level test socket for a semiconductor package having a non-pin grid array footprint. The present invention has particular applicability in testing a semiconductor package having either a land grid array footprint or a ball grid array footprint.
Bum-in boards are used to test semiconductor packages, such as integrated circuit (IC) chips, to ensure that the semiconductor packages are operating in a proper manner. Typically, the semiconductor package to be tested is inserted into a socket mounted on a burn-in board. For example, an IC chip is inserted into an IC socket on a bum-in board. The bum-in board is then placed in a testing chamber and power, ground and test signals are coupled to the bum-in board. The semiconductor packages in the IC chip are then tested for a period of time under stress conditions to ensure that the semiconductor packages are performing according to set standards or specifications.
As long as the semiconductor package has a pin grid array footprint, the semiconductor package can be placed directly into a pin grid array socket on the circuit board. However, semiconductor packages having non-pin grid array footprints, such as land grid array or ball grid array footprints are becoming more commonly employed. Problems arise when these non-pin grid array semiconductor packages need to be tested. In order to test such semiconductor packages, the footprint of the semiconductor package needs to be adapted for connection to the pin grid array socket. Therefore, a device such as an interposer, is used to convert the semiconductor package footprints. For example, a semiconductor package having a ball grid array footprint is inserted into an interposer having a pin grid array and the interposer is inserted into a pin grid array socket on a circuit board. However, using an interposer or other converting device creates a high profile with long electrical connections. Moreover, requiring an additional device unnecessarily increases the chance of a defective component and as a result, can damage the semiconductor package.
Therefore, there is a need for a system level test socket capable of receiving a semiconductor package having either a land grid array footprint or a ball grid array footprint, without requiring an additional component to convert the footprint.
There also exists a need for a simplified methodology for testing a semiconductor package having either a land grid array footprint or a ball grid array footprint, using a system level test socket on a circuit board, where the semiconductor package and socket have a low profile and short electrical paths between the semiconductor package and the circuit board.
These and other needs are met by embodiments of the present invention which provide method ad apparatus for testing a semiconductor package having either a land grid array footprint or a ball grid array footprint, without requiring an additional component to convert the footprint.
The test socket and method of using the socket of the present invention connect a semiconductor package having a non-pin grid array to a circuit board. The test socket includes a plurality of solder pads, wherein the solder pads are positioned to be aligned with corresponding leads from the non-pin grid array of a semiconductor package and a plurality of corresponding internal leads for connecting the plurality of solder pads to a plurality of leads on the bottom surface of the test socket. The test socket allows for the testing of semiconductor packages having non-pin grid array without having to use an interposer to convert the non-pin grid array. Also, the test socket allows for a lower profile since the interposer is not needed.
The testing system of the present invention includes a test socket for connecting a semiconductor package having a non-pin grid array to a circuit board. The test socket includes a plurality of solder pads, wherein the solder pads are positioned to be aligned with corresponding leads from the non-pin grid array of a semiconductor package and a plurality of corresponding internal leads for connecting the plurality of solder pads to a plurality of leads on the bottom surface of the test socket. The testing system includes one or more test sockets on a circuit board with a fastener for pressing a semiconductor package against a test socket. The testing system allows for a plurality of semiconductor packages having a non-pin grid array to be inserted into the test sockets on a circuit board and tested at the same time.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.